The present invention relates to an integrated circuit (IC) and a method of fabricating integrated circuits and more particularly to deep trench capacitors having an increased surface area.
A memory cell, such as a DRAM, in an IC comprises a transistor and an associated capacitor. The capacitor, which is typically formed in a portion of a trench, has a pair of conductive plates, i.e., electrodes, which are separated from each other by a node dielectric material. Information or data is stored in the memory cell in the form of charge accumulated on the capacitor. As the density of the ICs with memory cells increases, the area for the capacitor becomes smaller and the amount of charge the capacitor is able to accumulate is reduced. Thus, with less charge to detect, reading the information or data from the memory cell becomes much more difficult.
With a limited fixed space or volume for the capacitor of a memory cell in a highly integrated circuit, there are three known techniques for increasing the amount of charge within a fixed space or area. These three known techniques include: (1) decreasing the thickness of the dielectric material, i.e., node dielectric, that is located between the capacitor plates; (2) changing the dielectric material to one with a dielectric constant higher than SiO2 or Si3N4; or (3) increasing the surface area of the space to be used for the capacitor.
Of the above-mentioned techniques, solution (3) is the most viable because the other two solutions have drawbacks associated therewith. For example, solution (1), which thins the capacitor dielectric, also increases leakage currents that may affect the memory retention performance of the capacitor and the reliability of the memory cell. Solution (2), which purports to change the dielectric material to a higher-dielectric material, will only cause a slight improvement in charge storage because the dielectric constant of suitable alternative dielectrics in only slightly higher than the dielectric material currently being used. Moreover, the substitution of alternative dielectrics may be more complicated, more expensive and provide fabrication problems that are heretofore unknown. Accordingly, solution (3), i.e., increasing the surface area of the space to be used for the capacitor, provides the most promise for substantially improving the amount of charge stored without causing any of the problems mentioned for solutions (1) and (2) above.
One solution to increase the surface area of the capacitor is to replace common stack capacitor technology with trench capacitors. In common stack capacitor technology, the capacitor is built on a surface created on a semiconductor substrate. On the other hand, in trench capacitor technology, the capacitor is formed within a trench that is formed in a semiconductor substrate itself. An increase in depth of the trench increases the surface area of the capacitor. However, present fabrication methods and tools limit the depth of the trench. This problem is further compounded by the forever increasing density of ICs achieved by dimensional shrinkage. To offset the loss of surface area due to a reduction in width, the depth of the trench must be further increased to the point where the necessary depth is not achievable or becomes prohibitively expensive.
FIGS. 1A to 1E are sectional diagrams illustrating a method of fabricating a trench capacitor of a DRAM cell according to the prior art.
In FIG. 1A, a semiconductor substrate 100 is provided. A pad oxide layer 102 with thickness of about 200 angstroms is formed on the substrate 100 by oxidation. Subsequently, a pad nitride layer 104 with thickness of about 1600 angstroms is formed on the pad oxide 102 by low-pressure chemical vapor deposition (LPCVD). The pad oxide 102 and the paid nitride 104 constitute the pad layer 107. A first masking layer 108 such as boron-silicate glass (BSG) with thickness of 5,000 angstroms is formed on the pad layer 107 by CVD.
In FIG. 1B, the first masking layer 108 is defined as a mask to dry etch the pad layer 107 and the substrate 100 to form a deep trench 112 with depth of about 6 micron meters. Subsequently, the pad layer 107 is used as a stop layer to remove the first masking layer 108 by isotropic etching.
In FIG. 1C, a doped insulating layer 120 such as an arsenic-silicate glass (ASG) with thickness of 50 to 400 angstroms conformably covers the pad layer 107 and the sidewall and the bottom of the deep trench 112 by in-situ arsenic doped LPVCD. Subsequently, a first photoresist (PR) layer (not shown) is filled into the deep trench 112. The upper portion of the first photoresist layer is removed by PR stripping, and the remaining first photoresist layer is represented as the residual first photoresist layer 125′.
In FIG. 1D, the doped insulating layer 120 on the pad layer 107 and above the residual first photoresist layer 125′ in the deep trench 112 is removed by isotropic etching and the remaining doped insulating layer 120 is represented as a residual doped insulating layer 120′. Thereafter, the residual first photoresist layer 125′ is removed. An insulating layer 128 such as a tetraethyl orthosilicate (TEOS) oxide with thickness of 50 to 500 anstroms conformably covers the pad layer 107, sidewall of the deep trench 112 and surface of the residual doped insulating layer 120′ by LPCVD.
In FIG. 1E, after a drive-in process is performed, the arsenic ions in the residual doped insulating 120′ are driven into the substrate 100 to form junctions with depth of about 800 angstroms as a bottom electrode 130. Afterwards, the insulating layer 128 and the residual doped insulating layer 120′ are removed. A dielectric layer 140 is formed on the surface of the bottom electrode 130, and a conductive layer (not shown) such as a polycrystalline silicon in-situ doped with arsenic ions or phosphorus ions is then fully filled in the deep trench 112. A portion of the conductive layer in the deep trench 112 is removed, and a portion of the conductive layer surrounded by the dielectric layer 40 remains to form a top electrode 150. Accordingly, the manufacture of the trench capacitor of a memory cell is completed.
However, since the depth of the trench is limited by present fabrication methods and tools, there is a need to develop a new and improved method and capacitor which increases the surface area of the capacitor in deep trench memory cell without causing the substantial drawbacks mentioned in solutions (1) and (2) above.